1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a structure for maintaining an internal node, to which voltage of a constant level is transmitted, at a constant voltage level stably. More particularly, the present invention relates to a structure of an internal voltage down converter for down-converting an external power supply voltage to generate an internal power supply voltage.
2. Description of the Background Art
The size of elements in a semiconductor memory device which are the components thereof is reduced in accordance with increase in the density and degree of integration. The internal operating power supply voltage is decreased to improve reliability of such miniaturized elements, to increase the operation speed due to reduction in the signal amplitude on a signal line, and to reduce power consumption. In contrast, miniaturization is not so advanced in processors and logic LSIs (Large Scale Integrated circuit) which are external devices. When a process system is built using a semiconductor memory device, the system power supply voltage is determined depending upon the power supply voltage of such processors. In order to construct a system of a single power source, an external power supply voltage (system power supply voltage) is down-converted in a semiconductor memory device to a desired level to generate an internal power supply voltage. An internal voltage down converter is used to generate this internal power supply voltage.
FIG. 133 schematically shows a structure of a conventional internal voltage down converter. Referring to FIG. 133, an internal voltage down converter 10 includes a reference voltage generation circuit 4 for generating a reference voltage Vref at a constant level from an external power supply voltage VCE and ground voltage VSS, a comparison circuit 3 for comparing an internal power supply voltage VCI on an internal power supply line 5 with reference voltage Vref from reference voltage generation circuit 4, and a p channel MOS transistor 2 responsive to an output signal of comparison circuit 3 to supply current from an external power supply node (pad) to internal power supply line 5. Comparison circuit 3 receives an internal power supply voltage VCI on internal power supply line 5 at its positive input, and reference voltage Vref from reference voltage generation circuit 4 at its negative input. When internal power supply voltage VCI is higher than reference voltage Vref, the potential level of the output signal of comparison circuit 3 rises.
A load circuit 7 using this internal power supply voltage VCI is connected to internal power supply line 5. Load circuit 7 may operate with internal power supply voltage VCI as one operating power supply voltage. Also, load circuit 7 may generate a constant intermediate voltage (for example (VCI+VSS)/2) from internal power supply voltage VCI and ground voltage VSS. Load circuit 7 may also charge a predetermined signal line to the level of internal power supply voltage VCI (functioning as a sense amplifier, for example). Any of the above-described structures is allowed as long as load circuit 7 operates using internal powers supply voltage VCI. An operation of the internal power voltage down converter shown in FIG. 133 will be described hereinafter with reference to the waveform diagram of FIG. 134.
When internal power supply voltage VCI attains a constant voltage level (level of reference voltage Vref), the output signal of comparison circuit 3 attains a predetermined voltage level. When load circuit 7 operates and uses internal power supply voltage VCI, a current flowing from internal power supply line 5 to load circuit causes lowering in the level of internal power supply voltage VCI. In response, the voltage level of the output signal of comparison circuit 3 is lowered, which increases the conductance of a p channel MOS transistor (referred to as "drive transistor" hereinafter) 2. As a result, the current flow from external power supply node 1 to internal power supply line 5 increases. When the current flow via drive transistor 2 becomes greater than that consumed by load circuit 7, the level of internal power supply voltage VCI rises. When the level of internal power supply voltage VCI rises to become higher than reference voltage Vref, the voltage level of the output signal of comparison circuit 3 rises, and the conductance of drive transistor 2 is reduced. As a result, the current flow from drive transistor 2 to internal power supply line 5 is reduced or cut off. More specifically, when internal power supply voltage VCI is greater than reference voltage Vref, drive transistor 2 cuts off or reduces the supplying of current. When internal power supply voltage VCI becomes lower than reference voltage Vref, drive transistor 2 supplies a great amount of current from external power supply node 1 to internal power supply line 5. Thus, internal power supply voltage VCI is maintained at the level of reference voltage Vref.
According to a structure of an internal voltage down converter, a feedback loop is formed of drive transistor 2, internal power supply line 5, and comparison circuit 3. The adjustment of the level of internal power supply voltage VCI on the basis of this feedback includes the following steps:
(a) The output signal of comparison circuit 3 has a constant level at a normal state. It is assumed that this constant level is an H level (for example, the level of external power supply voltage VCE) where drive transistor 2 is completely turned off.
(b) Load circuit 7 operates to consume current from internal power supply line 5, whereby internal power supply voltage VCI is lowered.
(c) Comparison circuit 3 compares internal power supply voltage VCI with reference voltage Vref to reduce the level of an output signal thereof.
(d) Drive transistor 2 is turned on, whereby current is supplied from external power supply node 1 to internal power supply line 5.
(e) The level of internal power supply voltage VCI is restored.
(f) Comparison circuit 3 compares internal power supply voltage VCI with reference voltage Vref, whereby the voltage level of the output signal is increased.
(g) Drive transistor 2 is turned off.
According to the control using such a feedback loop, a change in internal power supply voltage VCI is detected by comparison circuit 3 to adjust the gate potential of drive transistor 2 according to the output signal of comparison circuit 3, whereby the supplying amount of current of drive transistor 2 is adjusted. There is a time delay between a change in internal power supply voltage VCI and adjustment of the supplying amount of current of drive transistor 2. This time delay will be described with reference to FIG. 135 schematically showing the relationship between internal power supply voltage VCI and an output signal of comparison circuit 3.
For the sake of simplification, FIG. 135 shows the state where the output signal of comparison circuit 3 is set at a constant voltage of an H level when internal power supply voltage VCI and reference voltage Vref become equal to each other.
The output signal of comparison circuit 3 is lowered shortly after the reduction in the level of internal power supply voltage VCI. This means that internal power supply voltage VCI is already varied greatly when the supplying amount of current of drive transistor 2 is increased according to the output signal of comparison circuit 3. A great amount of current is supplied from external power supply node 1 to internal power supply line 5 for the purpose of restoring the greatly varied internal power supply voltage VCI to its former voltage level (comparison circuit 3 has a differential amplifier structure, as will be described in detail afterwards). Although internal power supply voltage VCI is restored to the level of reference voltage Vref, the turn off of drive transistor 2 is delayed, so that internal power supply voltage VCI becomes higher than reference voltage Vref. As a result, overshooting occurs in internal power supply voltage VCI. This overshooting causes ringing due to the inductance component in internal power supply line 5, or causes reduction in the level of internal power supply voltage VCI due to the operation of load circuit 7. This state is repeated, and current is supplied from external power supply node 1 to internal power supply line 5 when drive transistor 2 attains an ON state.
In an ideal response waveform, current should be supplied to internal power supply line 5 via drive transistor 2 in immediate response to a change in internal power supply voltage VCI. In this case, the amount of change in internal power supply voltage VCI is small (due to a quick current supply timing), and internal power supply voltage VCI is restored to the former level of reference voltage Vref speedily. The amount of current through drive transistor 2 is small, and overshooting of a significant level will not occur. Internal power supply voltage VCI is restored to the level of reference voltage Vref stably.
By comparing the ideal response waveform and the operation waveform of a conventional internal voltage down converter, it is appreciated that an abrupt change in internal power supply voltage VCI in the structure of a conventional internal voltage down converter causes overshooting/undershooting in internal power supply voltage VCI. Therefore, a stable operation of load circuit 7 cannot be ensured.
Repetition of overshooting/undershooting causes a longer time period of the current supply through drive transistor 2, inducing a problem that the consumed current of the semiconductor device is increased. The time period of the flow of a great current is lengthened due to delay in the response of adjustment in the feedback loop, resulting in the problem that power consumption of the semiconductor device is increased. If the gate width (channel width) of a drive transistor 2 having a great current driving capability is set to a great value in order to compensate for the current consumed by load circuit 7 during operation, the gate capacitance is increased. Therefore, the gate potential of drive transistor 2 will not change immediately in response to the output signal of comparison circuit 3. Thus, the above-described problem of delay in response becomes significant.
Furthermore, when load circuit 7 operates and internal power supply voltage VCI changes abruptly, drive transistor 2 will be turned on in a delayed manner due to the delay in the response. Therefore, the voltage level of internal power supply voltage VCI is lowered significantly.
The above-described problem occurs, not only in an internal voltage down converter, but also in a feedback control system that feeds back an output signal that is to be maintained at a predetermined voltage level to a comparison circuit for controlling the level of the output signal according to the output signal fed back to the comparison circuit.
In operation of a load circuit, current is supplied from a power supply node thereof to an output node, whereby the signal of the output node is driven to the potential level on the power supply node. The voltage of the power supply node is varied due to this consumed current, resulting in generation of a power supply noise. Here, the level of the input and output signals of other circuits to which the current from that power supply node is provided are varied according to a change in the voltage of this power supply node, resulting in a problem that an erroneous operation is generated in the other circuits.
In a sense amplifier that consumes a great amount of current in charging/discharging a bit line during the operation of a semiconductor memory device, a change in the voltage of the power supply node causes reduction in the driving capability of the transistor of the sense amplifier (because the potential difference between the source and gate of a transistor is reduced). As a result, sense operation cannot be carried out at high speed. Furthermore, when this voltage change of the power supply node is great, the logic on the bit line is erroneously detected to cause an erroneous sensing operation.